vtr 9.0.0-1
Architecture: | x86_64 |
---|---|
Repository: | Extra |
Description: | Verilog to Routing -- Open Source CAD Flow for FPGA Research |
Upstream URL: | https://verilogtorouting.org |
License(s): | MIT |
Maintainers: |
Filipe Laíns |
Package Size: | 7.3 MB |
Installed Size: | 24.9 MB |
Last Packager: | Antonio Rojas |
Build Date: | 2025-06-14 18:06 UTC |
Signed By: | Antonio Rojas |
Signature Date: | 2025-06-14 18:19 UTC |
Last Updated: | 2025-06-14 18:20 UTC |